1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to the shape of a margin part of a gate electrode forming a MOS transistor which is provided on an active area having a concave part.
2. Description of the Background Art
A semiconductor device formed by MOS transistors is generally provided with an insulating film which is formed to enclose an active area (element forming region) for electrically isolating this active area from other ones. The gate electrode of each MOS transistor provided on the active area is formed over the active area and the insulating film to divide the active area, thereby electrically isolating source/drain regions formed on both sides of the gate electrode from each other.
FIG. 29 shows a part of an active area and gate electrodes which are formed on this active area. Referring to FIG. 29, the active area 1 has a concave part on its corner portion in a shape along a plan view. In other words, the concave part partially reduces the width of the active area 1. An insulating film 7 encloses the active area 1. The gate electrode 3 is so formed that its end portion reaches an upper portion of the insulating film 7 on the concave part, while the gate electrode 2 is so formed that its end portion reaches an upper portion of the insulating film 7 in a portion other than the concave part.
The parts of the gate electrodes 2 and 3 reaching the upper portion of the insulating film 7 are referred to as gate end caps, and x represents the length thereof. The gate end caps are set as margin parts (gate parts extending beyond the active area 1) in the layout design phase so that the length of the gate electrodes 2 and 3 are not smaller than the span of the active area 1, and the length x thereof is uniformly set for all gate electrodes as that from an edge portion of the active area 1 on design. This length x is so set that the forward end portions of the gate electrodes 2 and 3 are not located on the active area 1 even if the same are rounded due to corrosion by etching or the like to partially reduce the gate length. Source/drain regions SDA and SDB are formed on both sides of the gate electrode 3. While still another source/drain region is formed on a side of the gate electrode 2, symbol therefor is omitted in FIG. 29.
Such a gate end cap is defined as a part between an endmost portion of each gate electrode and an edge portion of the active area. When two active areas are formed separately from each other and a single gate electrode is formed to extend over these two active areas, therefore, the gate electrode is provided on an insulating film between the two active areas. However, no gate end cap is present on this portion, due to absence of an end portion of the gate electrode.
While such a gate electrode has an end portion on its pad part provided with a contact hole or a via hole or directly connected to a wiring layer, no gate end cap is present on (required for) this part.
The active area 1 has a concave part when provided with an AND-NOR gate C10 shown in FIG. 30, for example. Referring to FIG. 30, an AND part C1 is supplied with input signals I1 and I2, while a second input of a NOR part C2 is supplied with an input signal I3.
FIG. 31 shows the transistor level structure of the AND-NOR gate C10. The AND-NOR gate C10 comprises P-channel transistors Q1 and Q2 having source electrodes which are connected to a power source VDD in common, a PMOS transistor Q3 having a source electrode which is connected to drain electrodes of the P-channel transistors Q1 and Q2, NMOS transistors Q4 and Q6 having drain electrodes which are connected to that of the PMOS transistor Q3 in common, and an NMOS transistor Q5 having a drain electrode which is connected to a source electrode of the NMOS transistor Q4 and a source electrode which is grounded in common with that of the NMOS transistor Q6. The input signals I1 and I2 are supplied to gate electrodes G1, G2, G4 and G5 of the PMOS transistors Q1 and Q2 and the NMOS transistors Q4 and Q5, while the input signal I3 is supplied to gate electrodes G3 and G6 of the PMOS transistor Q3 and the NMOS transistor Q6. A common node between the PMOS transistor Q3 and the NMOS transistors Q4 and Q6 defines an output end.
FIG. 32 illustrates the layout of the NMOS transistors Q4 to Q6 of the AND-NOR gate C10 having such a structure.
Referring to FIG. 32, an active area AR is provided with a concave part on its corner portion in a shape along a plan view, and an insulating film IF encloses this active area AR. The gate electrode G6 is formed on a depressed region DR having a span which is reduced due to the concave part, while the gate electrodes G4 and G5 are formed on an ordinary region OR other than the concave part.
FIG. 33 is a sectional view taken along the line A—A in FIG. 29. As shown in FIG. 33, the gate electrode 3 formed on the active area 1 extends on the upper portion of the insulating film 7 over the length x of the gate end cap. Therefore, the source/drain regions SDA and SDB are electrically isolated from each other. While the active area 1 is invisible in the sectional direction since a channel region is formed on a portion of a silicon substrate 8 located under the gate electrode 3, FIG. 33 shows the position corresponding to the active area 1 with a broken line for convenience of illustration.
While the source/drain regions SDA and SDB are generally electrically isolated from each other regardless of the concave part of the active area 1, such source/drain regions SDA and SDB may not be completely isolated from each other, depending on the shape of the concave part.
This case is now described with reference to FIGS. 34 and 35. FIG. 34 shows an active area 1A having a corner portion which is provided with no concave part but obliquely notched. FIG. 36 is a sectional view taken along the line A—A in FIG. 34. As shown in FIG. 36, a gate electrode 3 does not reach an upper portion of an insulating film 7, and the active area 1A is longer than the gate electrode 3.
When gate electrodes 2 and 3 similar to those shown in FIG. 29 are formed on this active area 1A having such a shape, an end portion of the gate electrode 3 does not reach the upper portion of the insulating film 7. Source/drain regions are generally formed by injecting an impurity through a gate electrode serving as an injection mask. If an impurity is injected through the gate electrode 3 serving as an injection mask, therefore, source/drain regions SDA and SDB are formed not only on both sides of the gate electrode 3 but also around a forward end portion thereof. Consequently, the source/drain regions SDA and SDB formed on both sides of the gate electrode 3 are electrically shorted to hinder the function of the MOS transistor.
FIG. 35 shows an active area 1B provided on its corner portion with a concave part, which is not rectangularly shaped.
When gate electrodes 2 and 3 similar to those shown in FIG. 29 are formed on this active area 1B having such a shape, an end portion of the gate electrode 3 only partially reaches an upper portion of an insulating film 7. In this case, source/drain regions SDA and SDB formed on both sides of the gate electrode 3 are not electrically shorted but the gate length of the gate electrode 3 is partially reduced. Assuming that L represents the gate length of the gate electrode 3 and b represents the length of a part of the end portion of the gate electrode 3 not reaching the upper portion of the insulating film 7 as shown in FIG. 35, the substantial gate length is about L−b. When the gate length is thus partially reduced, a leakage current flows between the source/drain regions SDA and SDB in a transistor operation to deteriorate the function of the MOS transistor. FIG. 37 shows a gate electrode 3 having a forward end portion which is rounded due to corrosion by etching or the like. As shown in FIG. 37, both side surfaces of the gate electrode 3 only partially reach an upper portion of an insulating film 7 due to the rounded forward end portion. Assuming that b and c represent the lengths of such parts respectively, the substantial gate length is about L−b−c. Thus, the substantial gate length is further reduced as compared with a gate electrode having a forward end portion which is not rounded.
Formation of the active area 1A or 1B shown in FIG. 34 or 35 conceivably results from divergence of the insulating film from the layout design, an proximity effect in photolithography, displacement of the position for introducing the impurity from the planned one in formation of the source/drain regions SDA and SDB. It can be said that such a problem, which has become obvious following refinement of the semiconductor device, has heretofore been neglected.